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Module interrupt

Module interrupt 

Source

Constantsยง

CORE_INT_SRC_BASE ๐Ÿ”’
CORE_TIMER_INT_CTRL_BASE ๐Ÿ”’
ENABLE_IRQS_2 ๐Ÿ”’
IRQ_PENDING_2 ๐Ÿ”’
LOCAL_CONTROL_BASE ๐Ÿ”’
UART0_BASE ๐Ÿ”’
UART0_DR ๐Ÿ”’
UART0_FR ๐Ÿ”’
UART0_ICR ๐Ÿ”’
UART0_IMSC ๐Ÿ”’
UART0_IRQ_BIT ๐Ÿ”’
UART0_MIS ๐Ÿ”’

Staticsยง

KBD_FIFO
MOUSE_FIFO
UART_FIFO

Functionsยง

core_id ๐Ÿ”’
disable_interrupts
CPUๅ…จไฝ“ใฎIRQๅ‰ฒใ‚Š่พผใฟใ‚’็ฆๆญขใ—ใพใ™ (MSR DAIFSET)
enable_interrupts
CPUๅ…จไฝ“ใฎIRQๅ‰ฒใ‚Š่พผใฟใ‚’่จฑๅฏใ—ใพใ™ (MSR DAIFCLR)
init
init_secondary
rust_irq_handler