atmos/kernel/

sdio.rs

// sdio.rs - Arasan SDHCI SDIO driver for CYW43455 on RPi3B+
// WiFi chip (CYW43455) is connected via GPIO 34-39 to the Arasan eMMC2 controller.
#![allow(dead_code)]

// Arasan eMMC2 (SDIO for WiFi) base address on BCM2837
// Bus address 0x7E340000 -> CPU address 0x3F340000
const SDIO_BASE: usize = 0x3F340000;

// SDHCI register offsets
const SDHCI_DMA_ADDRESS: *mut u32 = SDIO_BASE as *mut u32;
const SDHCI_BLOCK_SIZE: *mut u16 = (SDIO_BASE + 0x04) as *mut u16;
const SDHCI_BLOCK_COUNT: *mut u16 = (SDIO_BASE + 0x06) as *mut u16;
const SDHCI_ARGUMENT: *mut u32 = (SDIO_BASE + 0x08) as *mut u32;
const SDHCI_TRANSFER_MODE: *mut u16 = (SDIO_BASE + 0x0C) as *mut u16;
const SDHCI_COMMAND: *mut u16 = (SDIO_BASE + 0x0E) as *mut u16;
const SDHCI_RESPONSE: *mut u32 = (SDIO_BASE + 0x10) as *mut u32; // 4x u32 at 0x10,14,18,1C
const SDHCI_BUFFER: *mut u32 = (SDIO_BASE + 0x20) as *mut u32;
const SDHCI_PRESENT_STATE: *mut u32 = (SDIO_BASE + 0x24) as *mut u32;
const SDHCI_HOST_CONTROL: *mut u8 = (SDIO_BASE + 0x28) as *mut u8;
const SDHCI_POWER_CONTROL: *mut u8 = (SDIO_BASE + 0x29) as *mut u8;
const SDHCI_BLOCK_GAP_CONTROL: *mut u8 = (SDIO_BASE + 0x2A) as *mut u8;
const SDHCI_CLOCK_CONTROL: *mut u16 = (SDIO_BASE + 0x2C) as *mut u16;
const SDHCI_TIMEOUT_CONTROL: *mut u8 = (SDIO_BASE + 0x2E) as *mut u8;
const SDHCI_SOFTWARE_RESET: *mut u8 = (SDIO_BASE + 0x2F) as *mut u8;
const SDHCI_INT_STATUS: *mut u32 = (SDIO_BASE + 0x30) as *mut u32;
const SDHCI_INT_ENABLE: *mut u32 = (SDIO_BASE + 0x34) as *mut u32;
const SDHCI_SIGNAL_ENABLE: *mut u32 = (SDIO_BASE + 0x38) as *mut u32;
const SDHCI_CAPABILITIES: *mut u32 = (SDIO_BASE + 0x40) as *mut u32;
const SDHCI_HOST_VERSION: *mut u16 = (SDIO_BASE + 0xFE) as *mut u16;

// SDHCI_PRESENT_STATE bits
const SDHCI_CMD_INHIBIT: u32 = 1 << 0;
const SDHCI_DATA_INHIBIT: u32 = 1 << 1;

// SDHCI_INT_STATUS bits
const SDHCI_INT_RESPONSE: u32 = 1 << 0;
const SDHCI_INT_DATA_END: u32 = 1 << 1;
const SDHCI_INT_ERROR: u32 = 1 << 15;

// SDIO command flags
const SDHCI_CMD_RESP_MASK: u16 = 0x03;
const SDHCI_CMD_CRC: u16 = 0x08;
const SDHCI_CMD_INDEX: u16 = 0x10;
const SDHCI_CMD_DATA: u16 = 0x20;
const SDHCI_CMD_RESP_SHORT: u16 = 0x02; // R1, R3, R4, R5, R6
const SDHCI_CMD_RESP_LONG: u16 = 0x01; // R2

// SDIO function numbers
pub const SDIO_FUNC_BUS: u8 = 0;
pub const SDIO_FUNC_BACKPLANE: u8 = 1;
pub const SDIO_FUNC_WLAN: u8 = 2;

// CYW43455 specific
const CYW43_BACKPLANE_FUNC: u8 = 1;
const CYW43_WLAN_FUNC: u8 = 2;

// CCCR (Card Common Control Register) addresses via SDIO CMD52
const CCCR_SDIO_REVISION: u32 = 0x00;
const CCCR_CCCR_REVISION: u32 = 0x00;
const CCCR_IO_ENABLE: u32 = 0x02;
const CCCR_IO_READY: u32 = 0x03;
const CCCR_INT_ENABLE: u32 = 0x04;
const CCCR_BUS_CONTROL: u32 = 0x07;
const CCCR_CARD_CAPABILITY: u32 = 0x08;
const CCCR_BUS_WIDTH: u32 = 0x07;

static mut SDIO_INITIALIZED: bool = false;

fn delay_us(us: u32) {
    for _ in 0..(us * 10) {
        unsafe { core::arch::asm!("nop") };
    }
}

fn delay_ms(ms: u32) {
    delay_us(ms * 1000);
}

unsafe fn wait_inhibit(data: bool) -> bool {
    let mask = if data {
        SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT
    } else {
        SDHCI_CMD_INHIBIT
    };
    let mut timeout = 100_000;
    while (core::ptr::read_volatile(SDHCI_PRESENT_STATE) & mask) != 0 {
        timeout -= 1;
        if timeout == 0 {
            return false;
        }
    }
    true
}

unsafe fn wait_int(mask: u32) -> bool {
    let mut timeout = 1_000_000;
    loop {
        let ints = core::ptr::read_volatile(SDHCI_INT_STATUS);
        if (ints & SDHCI_INT_ERROR) != 0 {
            core::ptr::write_volatile(SDHCI_INT_STATUS, ints);
            return false;
        }
        if (ints & mask) != 0 {
            core::ptr::write_volatile(SDHCI_INT_STATUS, ints & mask);
            return true;
        }
        timeout -= 1;
        if timeout == 0 {
            return false;
        }
    }
}

/// SDIO CMD52: Single byte read/write (no data transfer, uses SDHCI response)
/// fn=function, write=true for write, addr=register address, data=byte to write
/// Returns read byte on success.
///
/// # Safety
/// SDHCI MMIO レジスタへ直接アクセスする。SDIO コントローラが初期化済みで、
/// 同時に他コア/割り込みから SDHCI を操作していない状態で呼ぶこと。
pub unsafe fn cmd52(fn_num: u8, write: bool, addr: u32, data: u8) -> Option<u8> {
    if !wait_inhibit(false) {
        return None;
    }

    // Argument: [31]=R/W, [30:28]=func, [27]=RAW, [25:9]=addr, [7:0]=data
    let arg = (((write as u32) << 31)
        | ((fn_num as u32 & 0x7) << 28)) // RAW=0
        | ((addr & 0x1FFFF) << 9)
        | (data as u32);

    core::ptr::write_volatile(SDHCI_ARGUMENT, arg);
    // CMD52: index=52, response=R5 (short), no data
    let cmd = (52 << 8) | SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_INDEX;
    core::ptr::write_volatile(SDHCI_COMMAND, cmd);

    if !wait_int(SDHCI_INT_RESPONSE) {
        return None;
    }
    let resp = core::ptr::read_volatile(SDHCI_RESPONSE);
    // R5 response: bits[15:8]=flags, bits[7:0]=data
    Some((resp & 0xFF) as u8)
}

/// SDIO CMD53: Multi-byte block read/write
/// fn=function, write=direction, addr=start address, buf=data buffer, len=byte count
///
/// # Safety
/// SDHCI MMIO レジスタと DMA/PIO バッファへ直接アクセスする。SDIO コントローラが
/// 初期化済みで、`buf` が有効かつ排他的に使用できる状態で呼ぶこと。
pub unsafe fn cmd53(fn_num: u8, write: bool, addr: u32, buf: &mut [u8]) -> bool {
    let len = buf.len();
    if len == 0 || len > 512 {
        return false;
    }
    if !wait_inhibit(true) {
        return false;
    }

    // Block mode=0 (byte mode). WLAN function (func 2) is a FIFO — no addr increment.
    // Backplane function (func 1) accesses sequential memory — increment enabled.
    let addr_inc = fn_num != SDIO_FUNC_WLAN;
    let arg = (((write as u32) << 31)
        | ((fn_num as u32 & 0x7) << 28)
        | ((addr_inc as u32) << 26)) // block mode=0 (byte mode)
        | ((addr & 0x1FFFF) << 9)
        | (len as u32 & 0x1FF);

    core::ptr::write_volatile(SDHCI_BLOCK_SIZE, len as u16);
    core::ptr::write_volatile(SDHCI_BLOCK_COUNT, 1);
    core::ptr::write_volatile(SDHCI_ARGUMENT, arg);

    let xfer_mode: u16 = if write { 0x00 } else { 0x10 }; // bit4=data dir(1=read)
    core::ptr::write_volatile(SDHCI_TRANSFER_MODE, xfer_mode);

    let cmd = (53 << 8) | SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_INDEX | SDHCI_CMD_DATA;
    core::ptr::write_volatile(SDHCI_COMMAND, cmd);

    if !wait_int(SDHCI_INT_RESPONSE) {
        return false;
    }

    if write {
        // Write data to FIFO
        let mut i = 0;
        while i < len {
            let mut word: u32 = 0;
            for j in 0..4usize {
                if i + j < len {
                    word |= (buf[i + j] as u32) << (j * 8);
                }
            }
            core::ptr::write_volatile(SDHCI_BUFFER, word);
            i += 4;
        }
    }

    if !wait_int(SDHCI_INT_DATA_END) {
        return false;
    }

    if !write {
        // Read data from FIFO
        let mut i = 0;
        while i < len {
            let word = core::ptr::read_volatile(SDHCI_BUFFER);
            for j in 0..4usize {
                if i + j < len {
                    buf[i + j] = ((word >> (j * 8)) & 0xFF) as u8;
                }
            }
            i += 4;
        }
    }

    true
}

/// SDIO CLKを設定 (Arasan SDHCI clock divider)
unsafe fn set_clock(khz: u32) {
    // ベースクロック250MHzとして分周器を計算
    let base_khz = 250_000u32;
    let divisor = base_khz.div_ceil(khz).next_power_of_two().max(2);
    let div8 = (divisor >> 1) as u16;

    // Clock disable
    core::ptr::write_volatile(SDHCI_CLOCK_CONTROL, 0);
    delay_ms(1);

    // Internal clock enable + divisor
    let clk_ctrl = (div8 << 8) | 0x01; // bit0=internal clk enable
    core::ptr::write_volatile(SDHCI_CLOCK_CONTROL, clk_ctrl);

    // Wait stable
    let mut timeout = 10000;
    while (core::ptr::read_volatile(SDHCI_CLOCK_CONTROL) & 0x02) == 0 {
        timeout -= 1;
        if timeout == 0 {
            break;
        }
    }

    // SD clock enable
    let clk_ctrl = core::ptr::read_volatile(SDHCI_CLOCK_CONTROL) | 0x04;
    core::ptr::write_volatile(SDHCI_CLOCK_CONTROL, clk_ctrl);
    delay_ms(1);
}

/// SDIOコントローラの初期化とCYW43455の検出
pub fn init() -> bool {
    unsafe {
        crate::debug!("[FS] SDIO: Initializing Arasan eMMC2 controller...");

        // ソフトウェアリセット
        core::ptr::write_volatile(SDHCI_SOFTWARE_RESET, 0x07);
        let mut timeout = 100_000;
        while (core::ptr::read_volatile(SDHCI_SOFTWARE_RESET) & 0x07) != 0 {
            timeout -= 1;
            if timeout == 0 {
                crate::debug!("[FS] SDIO: Reset timeout");
                return false;
            }
        }
        delay_ms(10);

        // 電源ON (3.3V)
        core::ptr::write_volatile(SDHCI_POWER_CONTROL, 0x0F); // 3.3V + power on
        delay_ms(10);

        // 割り込み有効化 (ポーリング用)
        core::ptr::write_volatile(SDHCI_INT_ENABLE, 0x00FF_00FF);
        core::ptr::write_volatile(SDHCI_SIGNAL_ENABLE, 0);

        // タイムアウト設定 (最大値)
        core::ptr::write_volatile(SDHCI_TIMEOUT_CONTROL, 0x0E);

        // 初期CLK 400kHz (識別フェーズ)
        set_clock(400);
        delay_ms(5);

        // CMD0: GO_IDLE_STATE
        core::ptr::write_volatile(SDHCI_INT_STATUS, 0xFFFF_FFFF);
        core::ptr::write_volatile(SDHCI_ARGUMENT, 0);
        core::ptr::write_volatile(SDHCI_COMMAND, 0); // CMD0 (index 0 << 8), no response
        delay_ms(2);

        // CMD5: IO_SEND_OP_COND (SDIO discovery)
        core::ptr::write_volatile(SDHCI_INT_STATUS, 0xFFFF_FFFF);
        core::ptr::write_volatile(SDHCI_ARGUMENT, 0);
        core::ptr::write_volatile(SDHCI_COMMAND, (5 << 8) | SDHCI_CMD_RESP_SHORT);
        if !wait_int(SDHCI_INT_RESPONSE) {
            crate::debug!("[FS] SDIO: CMD5 failed (no SDIO device?)");
            return false;
        }
        let r4 = core::ptr::read_volatile(SDHCI_RESPONSE);
        let num_functions = (r4 >> 28) & 0x7;
        crate::debug!("[FS] SDIO: CMD5 R4=0x{:08X}, {} function(s)", r4, num_functions);

        // CMD5 with voltage: accept OCR
        let ocr = r4 & 0x00FF_FF00;
        core::ptr::write_volatile(SDHCI_INT_STATUS, 0xFFFF_FFFF);
        core::ptr::write_volatile(SDHCI_ARGUMENT, ocr);
        core::ptr::write_volatile(SDHCI_COMMAND, (5 << 8) | SDHCI_CMD_RESP_SHORT);
        if !wait_int(SDHCI_INT_RESPONSE) {
            crate::debug!("[FS] SDIO: CMD5 (OCR) failed");
            return false;
        }
        let r4 = core::ptr::read_volatile(SDHCI_RESPONSE);
        if (r4 & 0x8000_0000) == 0 {
            crate::debug!("[FS] SDIO: Card not ready (OCR=0x{:08X})", r4);
            return false;
        }

        // CMD3: SEND_RELATIVE_ADDR → RCA取得
        core::ptr::write_volatile(SDHCI_INT_STATUS, 0xFFFF_FFFF);
        core::ptr::write_volatile(SDHCI_ARGUMENT, 0);
        core::ptr::write_volatile(
            SDHCI_COMMAND,
            (3 << 8) | SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_INDEX,
        );
        if !wait_int(SDHCI_INT_RESPONSE) {
            crate::debug!("[FS] SDIO: CMD3 failed");
            return false;
        }
        let rca = (core::ptr::read_volatile(SDHCI_RESPONSE) >> 16) as u16;
        crate::debug!("[FS] SDIO: RCA=0x{:04X}", rca);

        // CMD7: SELECT_CARD (RCA)
        core::ptr::write_volatile(SDHCI_INT_STATUS, 0xFFFF_FFFF);
        core::ptr::write_volatile(SDHCI_ARGUMENT, (rca as u32) << 16);
        core::ptr::write_volatile(
            SDHCI_COMMAND,
            (7 << 8) | SDHCI_CMD_RESP_SHORT | SDHCI_CMD_CRC | SDHCI_CMD_INDEX,
        );
        if !wait_int(SDHCI_INT_RESPONSE) {
            crate::debug!("[FS] SDIO: CMD7 failed");
            return false;
        }

        // 高速CLK 25MHz に変更
        set_clock(25_000);
        delay_ms(5);

        // 4-bit bus width (CCCR BUS_IF: bits[1:0]=10 = 4-bit)
        cmd52(SDIO_FUNC_BUS, true, CCCR_BUS_WIDTH, 0x02);

        // HostControl: 4-bit mode
        let hc = core::ptr::read_volatile(SDHCI_HOST_CONTROL);
        core::ptr::write_volatile(SDHCI_HOST_CONTROL, hc | 0x02);
        delay_ms(2);

        // Function 1 (backplane) と Function 2 (WLAN) を有効化
        cmd52(SDIO_FUNC_BUS, true, CCCR_IO_ENABLE, 0x06); // bit1=F1, bit2=F2
        delay_ms(20);

        let ready = match cmd52(SDIO_FUNC_BUS, false, CCCR_IO_READY, 0) {
            Some(v) => v,
            None => {
                crate::debug!("[FS] SDIO: IO_READY read failed");
                return false;
            }
        };
        crate::debug!("[FS] SDIO: IO_READY=0x{:02X}", ready);
        if (ready & 0x06) != 0x06 {
            crate::debug!("[FS] SDIO: Functions not ready");
            return false;
        }

        SDIO_INITIALIZED = true;
        crate::debug!("[FS] SDIO: Controller initialized successfully.");
        true
    }
}

pub fn is_initialized() -> bool {
    unsafe { SDIO_INITIALIZED }
}